The present invention generally relates to integrated circuit (IC) device testing techniques, and more specifically, to using circuit structures to resolve random testability.
In today's environment, there are techniques available to execute the testing of a circuit design. The tests can be designed to test the integrity of the circuit design. Random patterns can be generated to produce inputs that are used to test for potential faults. Other techniques include using a brute force test which produces each and every combination of inputs for the test. However, as circuit designs become more and more complex, the number of patterns that need to be generated and tested can become prohibitive and unworkable.